Showing posts with label Power Electronics Project and Thesis. Show all posts
Showing posts with label Power Electronics Project and Thesis. Show all posts

Thesis on Advanced Single-Stage Power Factor Correction Techniques

Five new single-stage power factor correction (PFC) techniques are developed for single-phase applications. These converters are: Integrated single-stage PFC converters, voltage source charge pump power factor correction (VS-CPPFC) converters, current source CPPFC converters, combined voltage source current source (VSCS) CPPFC converters, and continuous input current (CIC) CPPFC converters.

Integrated single-stage PFC converters are first developed, which combine the PFC converter with a DC/DC converter into a single-stage converter. DC bus voltage stress at light load for the single-stage PFC converters are analyzed. DC bus voltage feedback concept is proposed to reduce the DC bus voltage stress at light load. The principle of operations of proposed converters are presented, implemented and evaluated. The experimental results verify the theoretical analysis.

VS-CPPFC technique use a capacitor in series with a high frequency voltage source to achieve the PFC function. In this way, the input inductor is eliminated. VS-CPPFC AC/DC converters are developed, and their performance is evaluated. VS-CPPFC electronic ballasts with and without dimming function are also presented. The average lamp current control with duty ratio modulation is developed so that the lamp operates in constant power with a low crest factor over the line variation. The experimental results verify the CPPFC concept.

CS-CPPFC technique employs a capacitor in parallel with a high frequency current source to obtain the PFC function. The unity power factor condition and principle of operation are analyzed. By doing so, the switch has less switching current stress, and deals only with the resonant inductor current. Design considerations and experimental results of the CS-CPPFC electronic ballast are presented.

VSCS-CPPFC technique integrates the VS-CPPFC with the CS-CPPFC converters. The circuit derivation, unity power factor condition and design considerations are presented. The developed VSCS-CPPFC converters has constant lamp operation, low crest factor with a high power factor even without any feedback control.

CIC-CPPFC technique is developed by inserting a small inductor in series with the line rectifier for the conceptual VS-CPPFC, CS-CPPFC and VSCS-CPPFC circuits. The circuit derivation and its unity power factor condition are discussed. The input current can be designed to be continuous, and a small line input filter can be used. The circulating current in the resonant tank and the switching current stress are minimized. The average lamp current control with switching frequency modulation is developed, so the developed electronic ballast operates in constant power, low crest factor. The developed CIC-CPPFC electronic ballast has features of low line input current harmonics, constant lamp power, low crest factor, continuous input current, low DC bus voltage stress, small circulating current and switching current stress over a wide range of line input voltage.

For Full Thesis Download:
Power Factor Correction Techniques.pdf

thesis on Adaptive Power and Rate Control in Third GenerationWideband CDMA Mobile Systems

This thesis proposes novel adaptive power control and rate change schemesand investigates the performance of a Wideband Code Division Multiple Access (W-CDMA)system in conjunction with these adaptive techniques. In these schemes, the transmit power and rate are adapted to the variations of the fading channel using adaptivethresholds based on the probability distribution function (pdf) of the predicted mobilechannel power values.We define a policy similar to the traditional power control technique withthresholds except that the thresholds are set based on several regions of operation in ourAdaptive Transmitter Power Control (TPC) and Adaptive Seamless Rate Change (SRC)schemes. These regions are defined by means of the probability distribution function(pdf) of the total average channel power. The pdf is initially constructed based on thehistory of the predicted channel power values derived from the long-range predictionalgorithm. These regions can be defined such that the system operates at a constant ratioof energy per bit over noise power.In a 1-user model with one channel path, the pdf of the channel power would bean exponential or chi-square function with 2 degrees of freedom. However, in a W-CDMAsystem, normally the rake receiver has several fingers. That is, at the receiver,the system either estimates or predicts the channel coefficients at each rake finger andperforms maximal ratio combining by multiplying each finger with its conjugate or chooses the ones with the highest energy and performs maximal ratio combining on theselected fingers.In a two-user system where the multi-access interference is modeled as theStandard Gaussian Approximation (SGA), the system performance and error probabilityof our W-CDMA system becomes similar to the one for our one-user system.Consequently, in a single user detector system, when all users adopt a similar policy fortheir adaptive power and rate control, the average total Multi-Access Interference (MAI)will be reduced. The resulting channel capacity of the system in this case will beincreased and the system may operate in a lower transmit power level.We evaluate the performance of these schemes using a detailed block diagramsimulation of a W-CDMA system. We model and simulate all major components of thesystem including an accurate model for realistic mobile channels. We present simulationresults to verify that the proposed novel schemes are superior to the traditionalapproaches for transmitter power control and rate change. Furthermore, our simulationresults show that our proposed techniques reduce the effect of Multi Access Interferencein a multi-user system.

Download full thesis From following Link:
Wideband CDMA Mobile Systems.pdf

An Impulse Generator Simulation Circuit

This thesis describes the creation of a simulation circuit to match the output of a Marx type Impulse Generator. The goal was to estimate the stray capacitance and insert that capacitance into the simulation circuit to effectively produce an output similar to that of the generator. An actual three-stage impulse generator was used as the base. Several different levels of impulse voltage were tested, and the output waveforms were captured. Research was conducted to formulate the stray capacitance and identify the locations of these capacitances in the generator itself. The simulation circuit was then subjected to several iterations, adjusting the capacitance values to attain an output as close as possible to that of the actual generator.
Conclusions of the research indicate that an effective simulation circuit can be created to give an output that is close to, but not exactly that of, the actual generator. In the research, several areas of error were identified in the actual generator that were not present in the simulation circuit. These areas are discussed in the thesis.

Download The Whole Project here:
http://www.mediafire.com/?2lmmdnmij24